`timescale 1ns / 1ps
/*
 Copyright 2020 Sean Xiao, jxzsxsp@qq.com
 
 Licensed under the Apache License, Version 2.0 (the "License");
 you may not use this file except in compliance with the License.
 You may obtain a copy of the License at
 
 http://www.apache.org/licenses/LICENSE-2.0
 
 Unless required by applicable law or agreed to in writing, software
 distributed under the License is distributed on an "AS IS" BASIS,
 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 See the License for the specific language governing permissions and
 limitations under the License.
 */

module yue_clint
(
    input  sys_clk,

    input  [ 31: 0 ] i_sft_int_v,
    input  [ 31: 0 ] i_timer_l,
    input  [ 31: 0 ] i_timer_h,

    output [ 31: 0 ] o_timer_l,
    output [ 31: 0 ] o_timer_h,

    input  [ 31: 0 ] i_tcmp_l,
    input  [ 31: 0 ] i_tcmp_h,

    input  [ 1: 0 ] i_timer_valid,
    input  [ 31:0 ] i_tm_ctrl,

    output o_mtip,
    output o_msip,

    input  i_rtcTick,

    input  rst_n
);
//===============================================================================
reg [ 31: 0 ] time_l;
reg [ 31: 0 ] time_h;
wire [ 63: 0 ] timer;
wire [ 31: 0 ] timecmp_l;
wire [ 31: 0 ] timecmp_h;
wire ipi_0;           //soft interrupt
// wire [13:0] waddr_bits_index;
// wire [13:0] raddr_bits_index;

//  wire        wr_cs;
//  wire        rd_cs;
//  wire        wr_en;
//  reg         b_cs;



//  assign    wr_cs=(m_waddr[31:16]==16'h0200);
//  assign    rd_cs=(m_raddr[31:16]==16'h0200);

//  assign s_awready = wr_cs;
//  assign s_wready  = s_awready&m_wvalid;
//  assign s_arready = rd_cs;
//  assign s_rvalid  = rd_cs;
//  assign s_bvalid  = m_arvalid&m_wvalid&s_wready;
//  assign s_brsp    = 2'b0;

assign o_mtip = ( { time_h, time_l } >= { timecmp_h, timecmp_l } ) ? 1'b1 : 1'b0;
assign o_msip = ipi_0;
assign timer  = { time_h, time_l } + 64'h1;

//  assign waddr_bits_index =m_waddr[15:2];
//  assign raddr_bits_index =m_raddr[15:2];


//  assign wr_en = m_awvalid &s_wready & m_wvalid;

//  always@(posedge sys_clk or negedge rst_n)
//  if(!rst_n) begin
//    b_cs<=1'b0;
//  end
//  else begin
//    if(wr_en)
//    b_cs<=1'b1;
//    else if(m_bready)
//    b_cs<=1'b0;

//  end

//  always@(*) begin
//  if(rd_cs)
//      case({raddr_bits_index[12],raddr_bits_index[1:0]})
//      0: s_rdata={{31'd0}, ipi_0};
//      1: s_rdata=32'b0;
//      2: s_rdata=time_l;
//      3: s_rdata=time_h;
//      4: s_rdata=timecmp_l;
//      5: s_rdata=timecmp_h;
//      6: s_rdata=32'b0;
//      7: s_rdata=32'b0;
//      endcase
//  end




//===============================================================================
always @( posedge sys_clk or negedge rst_n )
if ( !rst_n )
begin
    time_l <= 32'h0;
end
else
begin
    if ( i_timer_valid[ 0 ] )
        time_l <= i_timer_l;
    else if ( i_rtcTick & i_tm_ctrl[0])  // timer enable bit 0
        time_l <= timer[ 31: 0 ];
end



always @( posedge sys_clk or negedge rst_n )
if ( !rst_n )
begin
    time_h <= 32'h0;
end
else
begin
    if ( i_timer_valid[ 1 ] )
        time_h <= i_timer_h;
    else if ( i_rtcTick & i_tm_ctrl[0])
        time_h <= timer[ 63: 32 ];
end

assign timecmp_l = i_tcmp_l;
assign timecmp_h = i_tcmp_h;

//===============================================================================
//  always @(posedge sys_clk or negedge rst_n) begin
//    if (!rst_n) begin
//      timecmp_l <= 32'hFFFF_FFFF;
//    end
//    else if (wr_en & (waddr_bits_index==3'd4) ) begin
//      timecmp_l <=m_wdata;
//    end
//  end


//  always @(posedge sys_clk or negedge rst_n) begin
//    if (!rst_n) begin
//      timecmp_h <= 32'hFFFF_FFFF;
//    end
//    else if (wr_en & (waddr_bits_index==3'd5) ) begin
//      timecmp_h <= m_wdata;
//    end
//  end

assign ipi_0 = i_sft_int_v[ 0 ];
//  always @(posedge sys_clk or negedge rst_n) begin
//    if (!rst_n) begin
//      ipi_0 <= 1'h0;
//    end else begin
//      if((waddr_bits_index==3'd0)&wr_en)
//        ipi_0 <=  m_wdata ;
//      else
//        ipi_0 <=  {{31'd0}, ipi_0};

//    end
//  end

assign o_timer_l = time_l;
assign o_timer_h = time_h;


endmodule
